Linearized Di erential Transconductors in Subthreshold CMOS
نویسندگان
چکیده
Three schemes for linearizing the transconductance of the basic di erential pair in subthreshold CMOS are examined: 1) multiple asymmetric di erential pairs, 2) source degeneration via symmetric di usors, and 3) source degeneration via a single di usor. Using a maximally at optimizing criterion, the linear range of the basic di erential pair can be increased by four-to-eight times.
منابع مشابه
Transconductors in Subthreshold CMOS
| Four schemes for linearizing the transconductance of the basic di erential pair in subthreshold CMOS are examined. They are: source degeneration via (1) diode-connected transistors, (2) a single di usor and (3) symmetric di usors, and (4) multiple asymmetric di erential pairs. We derive equations for the di erential output current for each linearizing technique. We apply a maximally at optimi...
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